A fast FPGA implementation of the inter-layer deblocking filter for H.264/SVC

The scalable extension to H.264/AVC defines a coding scheme that organizes data in such a way that starting from a base layer increased spatial, temporal and quality detail can be obtained by the addition of successive information layers. In the case of spatial scalability a fundamental operation is inter-layer prediction which due to the block based nature of the algorithm originates block-edge discontinuities. To alleviate this problem the standard defines a block edge effect filter to smooth block boundaries . This work presents a novel filtering order aimed at speeding-up filter operation in the context of an FPGA-based implementation.